The present invention relates generally to semiconductor devices and more particularly to a semiconductor memory device having a control method that may suppress a potential reduction of a word line potential power supply upon word line selection.
A semiconductor memory device, such as a dynamic random access memory (DRAM), can have a memory cell formed by a memory cell transistor and a memory cell capacitor. The memory cell transistor is typically an n-type insulated gate field effect transistor (IGFET). The control gate of the memory cell transistor is connected to a word line, one source/drain terminal is connected to a bit line, and another source/drain terminal is connected to the memory cell capacitor. The memory cell capacitor stores charge indicative of the logic level of the bit stored in the memory cell. Because the potential of the source of an n-type IGFET is limited to a threshold voltage (Vt) below the potential applied to the gate of the n-type IGFET, the potential held on the memory cell capacitor is limited. In the case where a power supply voltage Vint is the maximum potential applied to a word line, the memory cell capacitor has a maximum potential of Vintxe2x88x92Vt, where Vt is the threshold voltage of the memory cell transistor. Thus, even if a data potential corresponding to the power supply Vint is applied to the bit line, a potential of Vintxe2x88x92Vt is stored on the memory cell capacitor. This can effect data integrity and/or refresh specifications.
To prevent the above-mentioned problem, the word line is typically supplied with a potential higher than the power supply voltage Vint. The potential higher than the power supply voltage Vint may be considered a word line activation potential. The word line activation potential can be the potential necessary to provide adequate charge transfer to and from the memory cell capacitor.
There are two approaches for obtaining a voltage higher than the power supply voltage Vint.
One approach uses an oscillator connected to a multiplying charge pump rectifier. The approach can constantly supply a boosted voltage.
Another approach is to use a bootstrapping capacitor, such that a bootstrapping pulse can be laid over a word line supplying potential.
Referring to FIG. 9, a block schematic diagram of a conventional DRAM is set forth and given the general reference character 100.
Conventional DRAM 100 includes a command decoder 101, which decodes a command received from a central processing unit (CPU) and provides a control signal to row control circuit 104. Also included is an address buffer 102 which receives an address signal and provides a row address to a word selection circuit 103 and a column address to a bit selection circuit 109. Command decoder 101 provides a row enable signal RE to the address buffer 102 and word selection circuit 103.
Conventional DRAM 100 includes an array of memory cells 110. Memory cells (for example, memory cell 113) are formed at the intersection of a bit line (for example, bit line 112) and a word line (for example, word line 111). Word selection circuit receives a boosted voltage VPP from a booster circuit 108 and based on the address value receive from address buffer 102 selects a word line 111 when the row enable signal RE becomes active. Boosted voltage VPP is applied to a selected word line 111.
A boosted potential detection circuit 106 receives the boosted potential VPP and detects whether or not boosted potential VPP falls below a predetermined potential. Boosted potential detection circuit 106 provides a boosted voltage signal VBUP to an oscillator circuit 107 and booster circuit 108. Oscillator circuit 107 provides an oscillation signal VBOS to the booster circuit 108.
Sense amplifier 114 detects a data signal on a row of selected memory cells (for example, memory cells connected to selected word line 111). Bit selection circuit 109 then selects a column (for example bit line 112) based on a column address received from address buffer 102. Thus, data is provided to or from the conventional DRAM 100 by way of input/output (I/O) buffer 115.
Referring now to FIG. 10, a circuit schematic diagram of boosted potential detection circuit 106 is set forth. Boosted potential detection circuit 106 is the boosted potential detection circuit 106 of FIG. 9.
Boosted potential detection circuit 106 has resistor devices (R101a and R101b) connected in series between boosted potential VPP and ground GND. Boosted potential VPP is connected to one terminal of resistor device R101a. One terminal of resistor device R101b is connected to ground GND. The other terminals of resistor devices (R101a and R101b) are connected to provide a potential to one input terminal of comparator circuit COM101. A reference potential Vs is supplied to the other input terminal of comparator circuit COM101. The boosted voltage signal VBUP is output from comparator COM101. The resistance values of resistor devices (R101a and R101b) are determined based on the values of the desired boosted potential VPP and reference potential Vs, so that when boosted potential is at a desired potential, a potential obtained at the connection point of resistor devices (R101a and R101b) is equal to the reference voltage Vs.
Referring now to FIG. 11, a circuit schematic diagram of oscillator circuit 107 is set forth. Oscillator circuit 107 is oscillator circuit 107 of FIG. 9.
Oscillator circuit 107 has a NAND gate NAND110 and inverters (IV111 to IV115). NAND gate NAND110 and inverters (IV111 to IV114) are connected in series to form a ring oscillator circuit with the output of inverter IV114 connected to an input of NAND NAND110. NAND gate NAND110 also receives boosted voltage signal VBUP at an input. Inverter IV115 is connected to receive the output of inverter IV114 as an input and provides the oscillation signal VBOS as an output.
When boosted voltage signal VBUP is at a high logic level, oscillator circuit 107 oscillates and the oscillation signal VBOS periodically changes logic level. However, when boosted voltage signal VBUP is at a low logic level, oscillator circuit 107 stops oscillating and the oscillation signal VBOS is maintained at a predetermined logic level (logic low).
Referring now to FIG. 13, a schematic diagram of booster circuit 108 is set forth. Booster circuit 108 is booster circuit 108 of FIG. 9.
Booster circuit 108 has transistors (Tr111 and Tr112), inverter IV116, boosting capacitor Cc and smoothing capacitor Cd. Power supply voltage Vint is connected to the gate and source of transistor Tr111. A drain of transistor Tr111 is connected to node a. Inverter IV116 receives oscillation signal VBOS as an input and provides an output to a terminal of boosting capacitor Cc at node b. Another terminal of boosting capacitor Cc is connected to node a. Transistor Tr112 has a source and gate connected to node a and a drain connected to smoothing capacitor Cd at node c. Boosted potential VPP is output at node c. Another terminal of smoothing capacitor Cd is connected to ground potential.
The operation of booster circuit 108 will now be described.
When the oscillation signal VBOS is at a logic high, node b is at a low potential. Node a is then precharged through transistor Tr111 to a potential of power supply voltage Vint minus Vt (a threshold voltage of transistor Tr111). When oscillation signal VBOS transitions to a logic low, node b transitions to a high potential (Vint). Node a is then boosted to 2Vint minus Vt. Diode configured transistor Tr112 then conducts and transfers charge from boosting capacitor Cc to smoothing capacitor Cd. Oscillation signal VBOS continues to oscillate and boosted potential VPP has a theoretical limit of (2Vintxe2x88x922Vt), where 2Vt is the combined threshold voltages of transistors (Tr111 and Tr112).
The boosted potential VPP can be increased by increasing the number of stages of transistor Tr112 and boosting capacitor Cc.
Referring now to FIG. 12, a timing diagram illustrating a boosting operation in the conventional DRAM 100 is set forth.
Referring to FIG. 12 in conjunction with FIG. 9, in conventional DRAM 100, when a command is input into command decoder 101, command decoder 101 decodes the command. If the command is a data read, data write, or refresh command, the command decoder outputs a control signal ACT/REF as a one-shot signal to the row control circuit 104. Row control circuit 104 outputs a row enable signal RE to activate the address buffer 102 and word selection circuit 103. During the time that the command is input into command decoder 101 an address signal is also input into address buffer 102. The address buffer 102 transmits the address to the word selection circuit 103 in synchronization with the rise of the row enable signal RE.
Referring now to FIG. 10, in the boosted potential detection circuit 106, the boosted potential VPP is input into one terminal of resistor device R101a. Resistance values of resistors (R110a and R101b) are chosen so that the potential at the connection node between the resistor devices (R101a and R101b) is VPP/2. Comparator COM101 compares the potential VPP/2 with the reference potential Vs. The reference potential Vs is set at 2.0V. When the potential VPP/2 is higher than the reference potential Vs (e.g. 2.0 V), boosted voltage signal VBUP is logic low. However, when the boosted potential VPP drops such that the potential VPP/2 falls below the reference potential Vs, boosted voltage signal VBUP is logic high. This indicates that the boosted potential VPP has fallen below the desired minimum potential of 4.0 V.
Referring again to FIG. 12, at a time before the command has been entered, it can be seen that boosted potential VPP falls below the minimum potential of 4.0V. Then, boosted voltage signal VBUP becomes logic high. Referring now to FIG. 11, oscillator circuit 107 receives the logic high boosted voltage signal VBUP. Oscillator circuit 107 is thus enabled. Thus, a time delay xcex94t1 after boosted potential VPP dips below the minimum potential (4.0V), oscillation signal VBOS begins to oscillate and booster circuit 108 begins to boost the boosted potential VPP. The time delay xcex94t1 is determined by the propagation delays of boosted potential detection circuit 106 and oscillation circuit 107.
After the command is received by command decoder 101, if the command is a data read, data write, or refresh command, the command decoder 101 outputs a control signal ACT/REF as a one-shot signal to the row control circuit 104. Row control circuit 104 outputs a row enable signal RE to activate the address buffer 102 and word selection circuit 103. During the time that the command is input into command decoder 101 an address signal is also input into address buffer 102. The address buffer 102 transmits the address to the word selection circuit 103 in synchronization with the rise of the row enable signal RE.
When word selection circuit 103 receives the active row enable signal RE, word selection circuit 103 electrically connects boosted power potential VPP to a word line (for example word line 111). A word line 111 is connected to a large number of memory cells. Thus, a word line has a relatively large word line capacitance Cw. This causes boosted power potential VPP to instantaneously drop, as illustrated in FIG. 12.
Accordingly, boosted potential detection circuit 106 outputs a logic high boosted voltage signal VBUP. A time delay xcex94t2 after the boosted potential VPP drops, oscillator circuit 107 begins to oscillate and provide an oscillating oscillation signal VBOS. Booster circuit 108 then begins to boost the boosted potential VPP. Thus, it can be seen that boosted potential VPP does not begin to recover until a time delay xcex94t2 after the boosted potential VPP drops. When boosted potential VPP becomes higher than 4.0V, the boosted voltage signal VBUP returns low and the oscillator circuit 107 and booster circuit 108 are disabled.
In recent years, the capacity of DRAMs continue to increase. As a result, the number of memory cells selected in one activation operation increases. Thus, a larger number of memory cells are provided with a boosted potential VPP on the control gates of the memory cell transistors. This increases the capacitance Cw loading the boosted potential VPP when memory cells are selected.
When a word line is selected, charge on smoothing capacitor Cd is transferred to the selected word line. This charge transfer causes the boosted potential VPP to drop as determined by the capacitance ratios between smoothing capacitor Cd and word line capacitance Cw as well as their respective potentials. Because of the time delay xcex94t2 before the boosted potential VPP begins to recover, a sufficient boosted voltage VPP can not be instantaneously obtained. When boosted voltage VPP becomes lower, the word line potential Vw recovers slowly to a proper level. This can effect the operating speed of the DRAM.
The voltage drop of boosted potential VPP can be decreased by increasing the capacitance value of smoothing capacitor Cd. However, this increases chip size, which in turn increases production costs.
An example of the second boosting method is illustrated in Japanese published Unexamined Patent Application No. Hei 5151773.
The second boosting method includes detecting the application of the Row Address Strobe (RASB) signal and temporarily boosting a potential RX supplied to the word line driver. However, because boosting is made temporarily utilizing a pulse, the boosted voltage level can vary greatly. Various factors can cause the fluctuation in the potential RX. Such factors include variations of: transistor characteristics, wiring resistances, parasitic capacitance, power supply voltages and temperatures, as just a few examples.
If the boosted voltage level (potential RX) is too high, stress on the memory cell can cause the cell transistor to degrade and the life of the semiconductor memory device is shortened. Alternatively, if the boosted voltage level is too low, a sufficient amount of charge cannot be supplied to the memory cell capacitor. Thus, data integrity becomes degraded and insufficient charge may be available for a read operation or the read operation may be delayed because it may take the sense amplifier longer to properly sense the differential voltage on a bit line pair. Also, the data in the memory cell will more rapidly degrade over time and the refresh period must be shortened.
Also, if the parasitic capacitance of the word line increases, a predetermined boosted voltage level cannot be achieved without increasing the boosting capacitance. The increased boosting capacitance must be driven by a large transistor. As a result of these factors, the chip size of the semiconductor memory device increases. Also, continuously charging and discharging large capacitors can create on-chip noise which can effect operations such as reading.
In view of the above discussion, it would be desirable to provide a semiconductor memory device having a control method capable of raising a word line potential without adversely affecting chip size. It would also be desirable to suppress the potential drop of a boosted potential when selecting a word line. It would also be desirable to reduce the time required to begin restoring the boosted potential and improve reading and writing speeds. It would also be desirable to reduce the occurrence of noise that may be generated from providing a boosted potential.
According to the present embodiments, a semiconductor memory device having boosted potential generation circuit is provided. The boosted potential generation circuit may provide charge to a boosted potential node when a word line is to be activated. The boosted potential generation circuit may include a boosting control circuit, a boosted potential detection circuit, an oscillator circuit, and a booster circuit. The boosting control circuit may generate a boosting control signal when a command decoder indicates that a word line may be activated. In response to the boosting control signal, the boosted potential detection circuit may enable the oscillator circuit so that the booster circuit may transfer charge to the boosted potential node. This may allow the boosted potential node to have adequate charge that may be provided to the word line when activated.
According to one aspect of the embodiments, a memory cell array may have a plurality of word lines and a word selection circuit may activate one of the plurality of word lines based on the value of an address. The boosted potential node may provide charge to the activated word line.
According to another aspect of the embodiments, the boosted potential generation circuit may detect a command to activate a word line and may provide charge to the boosted potential node before the word line is activated.
According to another aspect of the embodiments, the command to activate a word line may be a read, write or refresh command.
According to another aspect of the embodiments, a booster circuit may provide charge to the boosted potential node in response to an oscillation signal.
According to another aspect of the embodiments, a boosting control circuit may provide a one-shot boosting control signal indicating that a word line is to be activated.
According to another aspect of the embodiments, a boosted potential detection circuit may receive the boosting control signal and may provide a boosted voltage signal having an oscillator enable state and an oscillator disable state. The boosted voltage signal may have the oscillator enable state when the boosting control signal indicates that the word line is to be activated.
According to another aspect of the embodiments, the boosted voltage signal may have the oscillator enable state when the boosted potential node falls below a predetermined potential.
According to another aspect of the embodiments, the boosted voltage signal may have the oscillator enable state when the boosted potential is lower than a first predetermined potential when the boosting control signal does not indicate that the word line is to be activated. The boosted voltage signal may have the oscillator enable state when the boosted potential is lower than a second predetermined potential when the boosting control signal indicates that the word line is to be activated. The second predetermined potential may be greater than the first predetermined potential.
According to another aspect of the embodiments, the oscillator circuit may include an oscillating signal generator and an oscillator preset circuit. The oscillating signal generator may oscillate when the boosted voltage signal is in the oscillator enable state and the oscillator preset circuit may preset the oscillating signal generator to an opposite start state when the boosted voltage signal is in the oscillator disable state.
According to another aspect of the embodiments, an oscillation circuit may be coupled to generate an oscillation signal that may have periodic logic transitions when the boosted voltage signal is in the oscillator enable state. A booster circuit may be coupled to provide charge to the boosted potential node in response to logic transitions in the oscillation signal.
According to another aspect of the embodiments, a boosting control circuit may generate a boosting control signal in response to a control signal indicating that a word line is to be activated. The boosting control signal may be a one-shot pulse and a command decoder may receive an externally applied command and generate the control signal.
According to another aspect of the embodiments, the boosted potential detection circuit may include a comparator that can compare a reference potential and a boosted level indicating potential and may generate a boosted voltage signal having an oscillator enable state when the reference potential is greater than the boosted level indicating potential.
According to another aspect of the embodiments, the boosted potential detection circuit may generate the boosting control signal having a first boosting control logic state when a word line is to be enabled. The boosted potential detection circuit may generate the boosted voltage signal having the oscillator enable state when the boosting control signal has the first boosting control logic state.
According to another aspect of the embodiments, the boosted potential detection circuit may include a voltage divider circuit that may receive a boosted potential and provide a potential that is proportional to the boosted potential. A comparator may compare the proportional to the boosted potential and provide the boosted voltage signal based on the comparison.
According to another aspect of the embodiments, the boosted potential detection circuit may include first and second voltage divider circuits that may be selectable according to the logic value of the boosting control signal. This may enable the boosted potential node to have a higher potential when a word line is to be selected.
According to another aspect of the embodiments, a control method for controlling a semiconductor memory device having a booster circuit that may generate a boosted potential in response to an oscillation signal that may be generated by an oscillator circuit may include the following steps: receiving a command and an address, decoding the command, generating a boosting control signal in response to the decoded command indicating that a word line is to be activated, providing charge to a boosted potential node in response to the boosting control signal, providing an electrical connection between the boosted potential node and the word line in accordance with the value of the address received.
According to another aspect of the embodiments, the step of providing charge to the boosted potential node may provide a boosted potential greater than an activation potential of the word line.
According to another aspect of the embodiments, the step of generating a boosted control signal may include generating the boosted control signal having a one-shot pulse.
According to another aspect of the embodiments, the step of providing charge to a boosted node includes generating the oscillation signal having an oscillation signal period between logical transitions. The oscillation signal may be generated in response to the boosting control signal.
According to another aspect of the embodiments, generating the oscillation signal in response to the boosting control signal may include generating an oscillation control signal in response to the boosting control signal. The oscillation signal may have a last oscillation state when the oscillation control signal is in an oscillation disable state and the oscillation signal may transition to an opposite to last oscillation state when the control signal transitions to an oscillation enable state without being delayed by the oscillation signal period between transitions.